Meanwhile, many chip makers last week continued to lobby for a pair of initiatives-the Common Programming Interface (CPIX) and Common Switch Interface (CSIX)-that seek to define open standards for APIs and for the interface between CPU and switch fabric. They ran into resistance, however, from some key OEMs and possibly from Intel Corp., a fellow network processor player.
The trend toward commodity silicon could be accelerated by a similar wave of prepackaged software functionality. But dozens of ideas are hitting the market at once, many of them leading to chips that never existed before. The network processor alone is difficult to compare from one vendor to another, as evidenced by a discussion on potential benchmark criteria for the parts.
Meanwhile, embedded memory is shaping up as a must-have technology for the next generation of net processors: parallel-pipelined engines that handle packet classification at all seven layers of the Open Systems Interconnect protocol stack. That’s the path Silicon Access Networks is taking with a processor designed to handle OC-192c, a single 10-Gbit/second data stream. The startup hopes to move into production next year, and says it will roll out coprocessors in the meantime.
“It turns out that the embedding of the memory, instead of using external SRAM, gives you architectural benefits that allow you to do very deep packet processing in a very economical way,” said Rex Naden, vice president of marketing for Silicon Access.
Another startup, EZchip Technologies Ltd. (Migdal Heimek, Israel), is pursuing the same model, using a low-power embedded DRAM with wide bus interfaces on its network processor design. And executives at Xaqti Corp., now owned by Vitesse Semiconductor Corp., claim to have pitched the same architecture before EZchip arrived on the scene.
Silicon Access started life licensing embedded DRAM cell technology from foundry Taiwan Semiconductor Manufacturing Co., and used it to develop a fast memory core, capable of running at 133 MHz in random-access mode. At least four ASICs are being taped out now with Silicon Access DRAM on chip, said chief executive officer Perry Constantine.
But after realizing that its DRAM can be the enabler for high-speed packet processing, Silicon Access is leaving the core-licensing business and recruiting heavily out of Nortel and Newbridge Networks to refocus on communications. The company is up to 90 employees split between San Jose, Calif., and Ottawa.
Silicon Access plans to start slow, producing coprocessors to be offered up to existing net processor players. Those parts are expected to hit volume production late this year. By late 2001, the company hopes to be in volume production with its own network processor, the OC-192c design.
As the Silicon Access strategy suggests, coprocessors are likely to be an adjunct to the network processor craze, and a number of startups have begun announcing plans in this area. The idea is to off-load one particularly difficult problem-usually packet classification-from a net processor.
SwitchOn Networks Inc. (Milpitas, Calif.), which is developing a content-switching coprocessor called ClassiPI, this week announced an alliance with Sitera. The company already has a similar alliance in place with MMC Networks and in fact is working with every network processor vendor in an effort to gain recognition for its technology, said Subhash Bal, vice president of marketing.
“Something like this will take the market a while to understand. If you work with a few people who do understand the market, if you help them get to the market faster, everybody wins,” Bal said.
Those kinds of alliances might become more common as more types of networking chips emerge. “We see the market moving to a chip set mentality,” said Daniel Mayer, marketing director for Tachys Technologies (Paris), which described its switch fabric here last week. Mayer sees these alliances as a way for chip vendors to speed up acceptance of their products and combat the not-invented-here mentality of some switch OEMs. “Once there are whole chip sets available that are standards-based and credible, then I think there will be no other choice,” he said.
Tachys is developing a switch fabric based on the IEEE-1355 serial link standard, a mid-1980s precursor to the 1394 FireWire interface. “Lots of equipment manufacturers over the past year have been working on switching fabrics,” Mayer said, and many of them will think long and hard before replacing their proprietary parts with a merchant chip.
Coprocessor vendor Solidum Systems Corp. (Burlingame, Calif.) likewise is seeking alliances. On the heels of announcing strategic partnerships late last month with Sitera and QED, the company now says it plans to take the reins of CSIX and CPIX, in hopes of getting its technology written into those standards.
Originally part of the network processor camp, Solidum now concentrates on coprocessors for packet classification. To that end, Solidum and Vitesse will be working together to define interfaces that Solidum hopes can be passed by CPIX and CSIX.
“We are marshaling the industry around a common model and interface,” said Tim Feldhousen, Solidum’s director of marketing. “If a collection of vendors gets together and defines a standard, they can drive the industry.” Feldhousen hopes to have standards settled within a few months, a schedule he admits is ambitious, but one that would allow Solidum to include standardized interfaces with its next chip. But ongoing fireworks with some key industry figures could easily throw that schedule off track.
The application programming interfaces developed by the Common Programming Interface Forum are becoming an area of contention, particularly in regard to Intel’s relations with the rest of the net processor community. At the Intel Developer Forum in February, the company raised some eyebrows when it said it intended to use the so-called “ACE” APIs from its recent acquisition, NetBoost Inc., as the only common APIs for the Intel processors from Digital Semiconductor, Level One Communications and Softcom Microsystems.
At NetWorld+Interop, Rajiv Khemani of Intel’s NetBoost group turned up the heat when he made a point of saying his presentation on ACE would be “CPIX-free.” Khemani later said that Intel does not consider CPIX an open standard, a statement that elicited laughs and catcalls from the crowd. While the “classification” and “action” calls of the ACE environment appear to be a powerful way to abstract behavior, attendees last week said that Intel still needed to understand some realities of the market.
“Even if Intel was going to take a majority market share in network processors, rejecting open APIs would not be good politically,” said one software developer speaking off the record. “But at the rate they’re going, they’re not even going to have significant market share in routing and switching, which makes the closed-API concept sound just plain silly.”
But saying that Intel has rejected CPIX out of hand is unfair, according to Len Rand, Intel’s general manager for strategic marketing and global alliances, and former chief executive of NetBoost. Rand said that Intel’s customers already have begun asking for additions and changes to the NetBoost APIs. “They said, ‘We don’t care what you do about CPIX; just don’t take any bodies off what you’re doing for us,’ ” he said.
According to Rand, that put Intel in an awkward position: Should it finalize the nearly completed work on proprietary APIs, or drop it in favor of the incomplete CPIX spec? “CPIX makes sense, but there’s nothing coming out that we can evaluate to decide if we want to join that consortium or not,” Rand said.
While initial CPIX frameworks are anticipated by the end of the second quarter, they do not represent a full suite of the APIs that might be necessary for adjunct functions such as security and deep classification. Chrysalis-ITS Inc., for example, is developing a second set of APIs for its Luna network security processor, which must abstract different security-centric functions than those in CPIX.
Stephen Davis, security IC software manager at Chrysalis-ITS, said the Luna APIs will be designed in a layered format to work with more basic net processor APIs. Chrysalis-ITS plans to interface its API suite to both the CPIX and ACE camps, he said.
Intel is likewise seen as a thorn in the side of CSIX, founded by switch-fabric vendor Power X Ltd. (Sale, England) in an effort to devise a standard backplane interface between the switch fabric and the network processor.
Phil Mercer, chief executive officer of Power X, said that some of the net processor vendors gobbled up in the recent acquisition spree have confirmed that their support for CSIX will continue. In fact, what’s slowed CSIX development more than anything has been the gradual addition of new members, which turned many CSIX meetings into catch-up sessions for the newcomers, he said.
“The only guys [chip vendors] of any significance who aren’t members are Intel, and they still have apoplexy about joining other people’s standards initiatives,” Mercer said. In fact, he claimed, Intel’s systems group has shown interest in supporting CSIX.
Intel’s Rand said he wanted to champion the CSIX model to customers but met stiff resistance from switch vendors, who consider the backplane interfaces and switch fabric a competitive advantage. “As soon as a big customer comes and asks us for CSIX, we’ll give them CSIX,” he said. Mercer conceded that some switch vendors oppose CSIX. But he claimed that many more are embracing the concept as part of a general shift toward using merchant silicon.
“Two years ago, when I first went out on the road with Power X, we got 80 percent of the [potential clients] saying, ‘Why shouldn’t I do this myself?’ Now I think that number’s around 20 percent,” Mercer said. Nortel and Lucent are among the companies willing to consider a CSIX interface, he added.